EC708 Design and Modelling of Digital Systems

Course Name:

Programme:

M.Tech (VLSI)

Semester:

First

Category:

Programme Core (PC)

Credits (L-T-P):

(3-0-2) 4

Content:

Digital system design options and trade-offs, Design methodology and technology overview, High Level System Architecture and Specification: Behavioral modeling and simulation, Overview of FPGA architectures and technologies, Logic block architecture, Input and Output cell characteristics, clock input, Timing, Power dissipation, Programmable interconnect, Applications, Embedded system design using FPGAs, Dynamic architecture using FPGAs, reconfigurable systems, application case studies, Simulation / implementation exercises of combinational, sequential and DDigital system design options and trade-offs, Design methodology and technology overview, High Level System Architecture and Specification: Behavioral modeling and simulation, Overview of FPGA architectures and technologies, Logic block architecture, Input and Output cell characteristics, clock input, Timing, Power dissipation, Programmable interconnect, Applications, Embedded system design using FPGAs, Dynamic architecture using FPGAs, reconfigurable systems, application case studies, Simulation / implementation exercises of combinational, sequential and DSP kernels on Xilinx / Altera boards.SP kernels on Xilinx / Altera boards.

References:

Ming Bo Lin, Digital System Designs and Practices using Verilog HDL and FPGAs, Wiley, 2008

Brown and Vranesic, Fundamentals of Digital logic with Verilog Design, TMH, 2014

M. D. Ciletti, Advanced Digital Design with Verilog HDL, Pearson, 2010

W.Wolf, FPGA based system design, Pearson, 2005

Peter Ashenden, Digital Design, An embedded systems approach using Verilog, Elsevier, 2008

J. Bhaskar, A Verilog HDL Primer, BSP, 2008

Clive Maxfield, A design warrior’s guide to FPGAs, Elsevier, 2004

NPTEL Video Lectures

Department:

Electronics and Communication Engineering(ECE)

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